The present invention relates to computer systems and more particularly to computer system processors that support predication and perform predicate prediction.
A processor manipulates and controls the flow of data in a computer system. Increasing the speed or throughput of the processor will tend to increase the computational power of the computer. Processor designers employ many different techniques to increase processor speed and throughput to create more powerful computers for consumers. One technique used by designers is called predication.
Predication is the conditional execution of instructions depending on the value of a predicate. For example, consider the following sequence of instructions:
COMPARE R1=R2xe2x86x92p2
(p2) ADD R3+R4xe2x86x92R5
The first instruction, COMPARE R1=R2xe2x86x92p2, determines a value for the predicate p2 based on a comparison of the operands R1 and R2. If the value of register R1 is equal to the value of register R2, then the value of predicate p2 is set to xe2x80x9cTruexe2x80x9d, and if the values of R1 and R2 are not equal, then p2 is set to xe2x80x9cFalse.xe2x80x9d xe2x80x9cTruexe2x80x9d and xe2x80x9cFalsexe2x80x9d are typically represented in the processor as single bit values xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively, (or xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, respectively, in a negative logic implementation).
The second instruction, (p2) ADD R3+R4xe2x86x92R5, includes two parts. The first part, (p2), predicates (or conditions) the second part, ADD R3+R4xe2x86x92R5, on the value of predicate p2. If P is true (e.g. a xe2x80x9c1xe2x80x9d), then the value of R5 is set equal to the value of R3+R4. If p2 is false (e.g. a xe2x80x9c0xe2x80x9d), then the second part of the instruction is skipped (essentially treating the instruction like a no-op) and the processor executes the next sequential instruction in the program code sequence.
Unfortunately, the COMPARE instruction can take a long time to execute. Because of this, the execution of dependent, subsequent instructions, such as the ADD instruction, may be delayed until the COMPARE instruction completes execution. The present invention address this and other problems.
A method and apparatus for performing predicate prediction is described. In one method, the least significant bits (LSBs) of a first operand are compared to the LSBs of a second operand. The result of this comparison is used to determine a predicted predicate value for a predicate. A predicated instruction is then conditionally executed depending on the predicted predicate value.
Other features and advantages of the present invention will be apparent from the accompanying figures and the detailed description that follows.